The present invention relates to an ethernet controller memory management apparatus and its control method. More specifically, the present invention relates to an ethernet controller""s memory control equipment that stores received data from the ethernet controller in memory and its control method.
Communication networks such as computer networks are increasingly used in interconnecting a plurality of computers each of which independently executes tasks while communicating information over the network for shared use. The volume of information which may be transferred over such networks has increasingly become more demanding on the structure of the networks themselves. Various network devices are known to allow the connection of a greater number of computers to a single network and further to allow more free communication of information between computers or other devices on the network or on other interconnected networks. The protocols related to communication of information on a network typically further provide for checking whether or not various computers on the network are transmitting and/or receiving data within a single network or between different networks. Various hubs or repeaters are known which manage data exchanges within and between networks. As the number of devices on networks increases, the demands for high performance repeaters and other devices to meet the challenge of managing the information flow so that the data does not create a bottleneck effect on the network are increasingly required. Furthermore, the protocol supporting communications over such networks are typically evolving to support higher data rates and larger volumes of information transmittal over the communication networks.
One example of such a communication protocol is known as the ethernet protocol. FIG. 1 is a schematic diagram of a representative ethernet frame according to Institute of Electrical and Electronic Engineers (IEEE) 802.3 standard. Such ethernet networks typically use a Carrier Sense Multiple Access/Collision Detection (CSMA/CD) protocol as a collision detection and recovery mechanism. A CSMA/CD type computer (terminal) generally checks carriers on a transmission path of the network before transmitting frames. The computer then transmits a frame during what appears to the terminal to be an idle period on the transmission path. However, such networks allow collisions to occur when two different connected computers both attempt to transmit frames on the network at the same time. When the collision is detected, the ethernet protocol provides for collision recovery steps including stopping transmission of any remaining parts of a frame currently being transmitted and initiating retransmission of transmission frames which encounter the collision after some time interval which is typically specified by the collision detection recovery protocol in use on the network. Accordingly , as the CSMA/CD communication method involves the use of shared transmission media (or channels) the collision detection functions and the retransmission functions supporting frame transmission are preferably implemented in the physical layer and the data link layer of a multi-layer communications protocol as are known to those of skill in the art.
As shown in FIG. 1, an IEEE 802.3 ethernet frame generally includes a preamble, a starting frame delimiter (SFD), a destination address, a source address, a length or ethertype, information data, and a frame check sequence (FCS). The preamble is used to adjust bit synchronization to match the transmission and receiving speed of a transmitting device to the transmission and receiving speed of a receiving device. The SFD is a bit array used for frame synchronization which indicates the start of an available frame. The destination address indicates an address of a destination ethernet card controller to which the frame is to be transmitted. The source address indicates an address of the transmitting ethernet controller device. The length or ethertype indicates the length of information data contained in a frame or, alternately, determines ethernet types. The information data is the available data which is being communicated and may also contain padding, i.e., a portion filled with zeros (or ones) when the amount (length) of available data is less than a minimum length of a frame. The FCS is used to detect errors in a received frame, typically through the use of a check sum applied to the bits of the frame excluding the preamble and the SFD.
FIGS. 2a and 2b are schematic diagrams illustrating an ethernet controller respectively transmitting and receiving frames. Referring first to FIG. 2a, when transmitting data, a direct memory access (DMA) 2 in the ethernet controller reads data to be transmitted from a memory 1 and transmits the data to a media access control (MAC) 3 which is typically a sub-layer of the data link layer. The MAC 3 in turn transmits the data to the physical layer, adding the preamble, SFD, padding, and FCS. The central processing unit (CPU) (not shown) then typically provides predefined addresses of the transmitting device and the receiving device, which are stored in memory, to the DMA 2 during data transmission.
Referring to FIG. 2b, when receiving data, the MAC 3xe2x80x2 transmits the data received from the physical layer to the DMA 2xe2x80x2, typically excluding the preamble and SFD. The DMA 2xe2x80x2 stores the received data in the memory 1xe2x80x2 without requiring help from the CPU (not shown).
The CPU reports an address of the data to be transmitted and a storage address of the received data respectfully to the DMA 2, 2xe2x80x2 through a frame descriptor at the time of transmitting and/or receiving data. More particularly, the frame descriptor is typically assigned to an associated memory location by the CPU, and read through the use of a frame descriptor pointer.
FIG. 3 is a schematic diagram illustrating a frame descriptor which may be used with existing ethernet controllers. The illustrated single frame descriptor 5 is mapped into a frame at the time of transmitting and/or receiving data. As shown in FIG. 3, the frame descriptor 5 includes a data pointer 5a, a status field 5b, a length field 5c, a control field 5d and a descriptor pointer 5e. The data pointer 5a may be a 32-bit pointer to indicate a first or starting address of a memory location where data received or to be transmitted is stored in memory. The status field 5b has bits to indicate a status of transmission and receiving and which may further indicate error types. The length field 5c indicates a length (amount) of data contained in the frame to be transmitted and/or received. The control field 5d is used to assign methods to transmit and receive frames. The descriptor pointer 5e has an address of a next frame descriptor which is next to (sequentially linked to) the current frame descriptor 5. In other words, a plurality of frame descriptors may be provided with a linked list sequential structure.
FIG. 4 is a schematic diagram representing operations related to the transmission and/or receipt of data over an ethernet protocol network using a frame descriptor as described with reference to FIG. 3 in the ethernet controller. As shown in FIG. 4, the frame descriptor pointer 10, independently from the frame descriptors 20 through 22, manages a plurality of frame descriptors 20, 21, 22 which are associated in a linked list structure. That is, the frame descriptor pointer 10 contains the address of the currently operative frame descriptor 20, and, when the current frame descriptor 20 is utilized to store or retrieve data for communication, the address contained in the frame descriptor pointer 10 is updated with a value of a descriptor pointer 20e, that is, a value indicating the address of a frame descriptor 21 coupled sequentially next to the current frame descriptor 20. As noted above, a plurality of frame descriptors 20 through 22 are allocated in predetermined areas of memory as a linked list structure by the CPU. At this time, the frame descriptor pointer 10 indicates the first frame descriptor.
Data to be transmitted are generally configured (located) in the memory 30 when received by the ethernet controller for transmission. However, during the reception of data from the network, predetermined uniform spaces, typically each of which is 1518-bytes long (the maximum length of data information in a frame), are allocated in order to store the received data.
Operations according to the ethernet controller of FIG. 4 will now be described. When transmitting data, the data to be transmitted is configured in the memory 30. A first address of the data to be transmitted is set in the data pointer 20a of the frame descriptor 20, and a length field 20c is set to the length of the data to be transmitted. The descriptor pointer 20e is set to an address of a frame descriptor 21 which is coupled next to the current frame descriptor 20 in the linked list structure. Finally, a transmission control bit of the control field 20d is set so that the data will be transmitted through the ethernet controller. When the data transmission is completed, a bit indicating the result of the transmission is typically set in status field 20b, and the frame descriptor pointer 10 is updated with a value of the descriptor pointer 20e in preparation for a next transmission.
When receiving data, the data input from the MAC 3xe2x80x2 are received in association with the frame descriptor 20 which is identified by the frame descriptor pointer 10. That is, the received data is stored in the memory 30 area identified by the starting address contained in data pointer 20a. At this time, the length field 20c is set as the length of the received data, and the status field 20b shows the results of this data reception. When the data transmission is completed, the frame descriptor pointer 10 is updated with a value of the descriptor pointer 20e so as to point to the next frame descriptor 21. Operations repeat similarly with descriptor pointer 21e of frame descriptor 21 pointing to the next frame descriptor 22.
At this point, as the length of the data being transmitted generally cannot be known ahead of time. Therefore, the maximum receiving length is typically set in advance. The maximum length under the IEEE 802.3 standard is 1518 bytes. Therefore, the memory is allocated ahead of time into 1518-byte slots which are identified and sequentially linked using the frame descriptors 20, 21, 22. In other words, the start addresses of the allotted memory blocks are respectively set in the data pointer fields 20a, 21a, and 22a of the frame descriptors 20 through 22. For example, as shown in FIG. 4, when an address 1000 is set in the data pointer field 20a of the first frame descriptor 20, an address 2518 (which is 1518 bytes away from the first address) is set in the data pointer 21a of the second frame descriptor 21.
A disadvantage of this previously proposed memory management system is, that in the event that the length of data received in a frame is short (i.e., only 64 bytes), this data is stored in memory starting from the address 1000 (or the beginning of the memory area allotted for the first data element), and the remainder of the allotted memory in the block (area except these 64 bytes) will typically be unused. The next received frame data will be stored in memory beginning at the address 2518, the area of memory allotted to the second data element, and, therefore, there will be unused memory. In the event that the lengths of received data are short, the above-mentioned unused areas can be much larger than the used areas, so that memory is wasted.
It is, therefore, an object of the present invention to provide systems and methods for managing ethernet controller memory which may decrease memory loss and enhance memory management.
In order to provide for the foregoing and other objectives, ethernet controller memory management systems and methods for memory management for an ethernet controller are provided which allocate blocks of memory based on the amount of data contained in the received ethernet frame. A linked list structure of frame descriptors is utilized for establishing the sequential blocks of allocated memory for data storage, however, the data pointers indicating the starting location of each sequential block of memory are dynamically updated through the use of a frame link detector circuit and methodology which establishes the correct pointer address in a next frame descriptor field based on adding a calculated length of the received data to an initial starting point memory address for the current frame descriptor memory block. Accordingly, the amount of memory allocated to reflect a respective frame descriptor for a particular received frame is limited to the necessary amount of memory to store the length of data received in the respective frame. Therefore, the prior art potential problem of a significant amount of unused memory may be overcome by the systems and methods of the present invention.
In one embodiment of the present invention, an ethernet controller memory management system is provided including a frame position detector circuit operable to detect a frame position of a length field value from a received frame and a frame length detector circuit operable to read the length field value and to output a memory address for a next frame based on the length field value and a current memory address. The frame position detector circuit may include a frame start detector operable to detect a starting reference location within the received frame and a counter initialized responsive to the frame start detector and operable to count received frame units within the received frame.
In another embodiment of the present invention, the system further includes a buffer memory operable to store the current memory address and the memory address for a next frame and an update controller operable to output a bus request signal to a central processing unit (CPU) responsive to a first control signal from the frame length detector circuit and to output a second control signal to initiate output of the memory address for a next frame to a data bus responsive to a bus admit signal from the CPU. The buffer memory may also store the received frame. In addition, a linked list of memory location pointers may be provided for use in sequentially storing received frames. In this embodiment, the current memory address is contained in a first one of the memory location pointers and the memory address for a next frame is output to a next one of the memory location pointers in the linked list of memory location pointers. The received frame may include a frame descriptor and further frame may be an IEEE 802.3 protocol compliant ethernet frame received from an ethernet protocol network. The linked list may be a linked list of frame descriptors each of which includes an associated memory location pointer, a length field configured to indicate the length of an associated received frame and a pointer field to a next frame descriptor in the linked list of frame descriptors. In one embodiment, the frame descriptor further includes a status field to indicate status of the received frame and a control field to control receiving of the received frame.
In a further embodiment of the present invention the length field value is positioned within the frame descriptor a predetermined number of frame units after the starting frame delimiter. The frame start detector is operable to detect the starting frame delimiter and the frame length detector circuit is operable to read the length field value responsive to the counter having a value corresponding to the predetermined number of frame units.
In a further aspect of the present invention, methods and systems are provided for memory management for an ethernet controller. An ethernet frame is received which includes a length field value. The length field value of the received ethernet frame is read and a memory address for a next frame is generated based on the length field value and an associated memory address of the received frame. The length field value in one embodiment is read by initializing a counter responsive to a starting reference location in the received ethernet frame, incrementing the counter responsive to sequential frame units within the received ethernet frame and reading the length field value when the counter is incremented to a predetermined number associated with a position of the length field value in the received ethernet frame. The memory address for a next frame may be generated by summing the associated memory address of the received frame and the length field value.
In a further embodiment of the present invention, the memory management system determines whether the field length value has been successfully read and sets the memory address for a next frame to a predetermined address responsive to the determining step when the field length value is not successfully read. In this embodiment, the generation of the memory address for the next frame by summing is performed responsive to the determining step if the field length value is successfully read.
In another embodiment of the present invention, a next frame is received and stored at the memory address for a next frame. The storing may be provided by outputting a bus request signal to a CPU after the memory address for the next frame is generated, receiving a bus admit signal from the CPU and updating a pointer to the memory address for a next frame including placing the memory address for a next frame on a data bus and an address of the pointer on an address bus. In one embodiment, updating is performed using direct memory access (DMA) without operation of the CPU.